1. Field of the Invention
This invention generally relates to an integrated circuit wafer dicing method, wherein a plurality of integrated circuit dies are formed from an integrated circuit wafer by the integrated circuit wafer dicing method.
2. Description of the Prior Art
A wafer is a substrate for manufacturing integrated circuits. Using integrated circuit fabrication technology, through a series of complicated chemical, physical, and optical processes, a fabricated integrated circuit wafer can include thousands or hundreds of integrated circuit dies. After being tested, cut, and packaged, these dies can be formed into various integrated circuit products having different functions.
FIG. 1 shows a conventional integrated circuit wafer 900 and an enlarge view of the area 80; FIG. 2 shows a cross-sectional view of the area 80 of FIG. 1 indicated by PP. As shown in FIGS. 1 and 2, the conventional integrated circuit wafer 900 includes a wafer substrate 100, a plurality of integrated circuits 300, and a plurality of test-keys 400. In a conventional wafer dicing process, an external force K is applied by a cutter to the integrated circuit wafer 900 along a path between two adjacent integrated circuits 300. Because the cutter is directly applied onto the integrated circuit wafer 900, cracks and damages of the integrated circuit wafer 900 will be produced due to the dicing stress. On the other hand, the test-keys 400 are distributed between the integrated circuits 300, i.e. on the dicing path. Therefore, the yield rate will be decreased due to metal ashes generated from the cutting of test-keys during the dicing process. Therefore, it is desired to improve the conventional dicing method.